The present disclosure relates to a semiconductor structure, and more particularly to a semiconductor structure including a fin field effect transistor and a planar field effect transistor having different crystallographic orientations for channels, and a method of manufacturing the same.
A planar field effect transistor is a field effect transistor including a channel that underlies a horizontal surface of a semiconductor material in contact with a gate dielectric. A fin field effect transistor is a field effect transistor including at least one channel located directly underneath a substantially vertical sidewall of a semiconductor fin.
Conventional integration schemes for forming fin field effect transistors provide n-type fin field effect transistors and p-type fin field effect transistors having the same crystallographic orientations for the surfaces of the channels, i.e., substantially vertical surfaces that contact gate dielectrics. For the purpose of maximizing the on-current of fin field effect transistors, it may be desirable to form an n-type field effect transistor in a semiconductor material layer having a (100) top surface, and to form a p-type field effect transistor in another semiconductor material layer having a (110) top surface. Further, it may also be desirable to employ different semiconductor materials for an n-type field effect transistor and for a p-type field effect transistor in order to provide high on-current for each type of fin field effect transistors.